高k栅介质SOI应变硅肖特基源漏MOSFET漏致势垒降低效应研究

The Research of Drain Induced Barrier Lower Effect for SOI Strained Silicon Schottky Source/Drain MOSFET with High-k Gate Dielectric

摘要:

高k栅介质SOI应变硅肖特基源漏MOSFET结合了应变硅工程、高k栅介质、SOI结构和肖特基源漏四者的优点，是一种实现小尺寸MOSFET的潜力器件.通过求解二维泊松方程建立了该结构的阈值电压模型，模型中考虑了镜像力势垒和小尺寸量子化效应对源漏极的电子本征肖特基势垒高度的影响，在阈值电压模型基础上获得了漏致势垒降低模型.从文献中提取漏致势垒降低的实验数据与模型进行对比，验证了其正确性，随后在此基础上讨论分析了漏致势垒降低和各项参数的变化关系.结果表明，漏致势垒降低随应变硅层厚度的变厚、沟道掺杂浓度的提高和锗组分的增大而增大，随沟道长度的变长、栅介质介电常数的增大、电子本征肖特基势垒高度的提高和漏源电压的增大而减小.适当调节模型参数，该结构可很好的抑制漏致势垒降低效应，对高k栅介质SOI应变硅肖特基源漏MOSFET器件以及电路设计具有一定的参考价值.

Abstract:

The SOI strained silicon schottky source/drain MOSFET with high-k gate dielectric is a potential device realizing small size MOSFET, which combines the advantages of strained silicon engineering, high-k gate dielectric, SOI structure and schottky source/drain. A model for the structure is proposed by solving two dimensional Possion’s equation, which takes into account for the impact on the source/drain schottky barrier height for electron of image force barrier and size quantization effect, then the drain induced barrier lower model is investigated based on the threshold voltage model. The experiment data of drain induced barrier lower extracted from literature is compared with the model, which verifies its correctness, and discuss the variety relationship between drain induced barrier lower and several parameters. The result shows that drain induced barrier lower increases with strained silicon thickness, channel doping and germanium fraction increasing, decreases with channel length, gate dielectric constant, intrinsic schottky barrier height for electron and drain source voltage increasing. The device can suppress drain induced barrier lower effect greatly through adjusting the model parameters properly, which can provide some reference for the design of SOI strained silicon schottky source/drain MOSFET with high-k gate dielectric device and circuit.